CHIP   MAIN   GAL22V10

/* Right GAL (Main logic) for SYS-Check V2.1      12/2014 by tfhh        */
/*                                                                       */
/* 3rd place at ABBUC hardware contest 2014                              */

A15   A14  A13   A12   A11   PB7   PHI2  PHI2S  RW   OSSEL  MEMSEL  GND
EMEM  EOS  OSCS  RCS1  RCS2  RWE   ROE   FWE    REF  HIAD   PB0     VCC
 
/HIAD = PHI2S * /RW * A15 * A14 * /A13 * A12 * /A11;                     /* write access to $D0xx-$D7xx as combined signal for GAL 1 */

/ROE  = PHI2S * RW;                                                      /* OutputEnable for SRAMs and Flash/EPROM/ROM */

/RWE  = /RCS1 * /RW * PHI2S                                              /* WriteEnable for SRAMs */
      + /RCS2 * /RW * PHI2S;

/FWE = /OSCS * /RW * PHI2S;                                              /* WriteEnable for Flash-ROM */

/RCS1 = EMEM * /MEMSEL * /A15 * /A14                                     /* ChipEnable 1st 32k SRAM ($0000-$3FFF) */
      + EMEM * /MEMSEL * /A15 *  A14 * /A13 * /A12                       /* ChipEnable 1st 32k SRAM ($4000-$4FFF) */
      + EMEM * /MEMSEL * /A15 *  A14 * /A13 *  A12 * /A11 * PB7 * PB0    /* ChipEnable 1st 32k SRAM ($5000-$57FF) */
      + EMEM * /MEMSEL * /A15 *  A14 * /A13 *  A12 * /A11 * /PB0         /* ChipEnable 1st 32k SRAM ($5000-$57FF) */
      + EMEM * /MEMSEL * /A15 *  A14 * /A13 *  A12 *  A11                /* ChipEnable 1st 32k SRAM ($5800-$5FFF) */
      + EMEM * /MEMSEL * /A15 *  A14 *  A13;                             /* ChipEnable 1st 32k SRAM ($6000-$7FFF) */

/RCS2 = EMEM * /MEMSEL * A15 * /A14                                      /* ChipEnable 2nd 32k SRAM ($8000-$BFFF) */
      + EMEM * /MEMSEL * A15 *  A14 * /A13 * /A12 * /PB0                 /* ChipEnable 2nd 32k SRAM ($C000-$CFFF) */
      + EMEM * /MEMSEL * A15 *  A14 * /A13 *  A12 * A11 * /PB0           /* ChipEnable 2nd 32k SRAM ($D800-$DFFF) */
      + EMEM * /MEMSEL * A15 *  A14 *  A13 * /PB0;                       /* ChipEnable 2nd 32k SRAM ($E000-$FFFF) */

/OSCS = PB0 * EOS * /OSSEL *  A15 * A14 *  A13                           /* ChipEnable EPROM, range $E000-$FFFF */
      + PB0 * EOS * /OSSEL *  A15 * A14 * /A13 *  A12 *  A11             /* ChipEnable EPROM, range $D800-$DFFF */
      + PB0 * EOS * /OSSEL * /A15 * A14 * /A13 *  A12 * /A11 * /PB7      /* ChipEnable EPROM, range $5000-$57FF */ 
      + PB0 * EOS * /OSSEL *  A15 * A14 * /A13 * /A12;                   /* ChipEnable EPROM, range $C000-$CFFF */

/REF = /RCS1 + /RCS2 + /OSCS;                                            /* drag REFRESH down to deactivate ATARIs internal mapping */

/* input pin PHI2 is actually unused, because I change term /ROE from PHI2 to PHI2S. It seems to be more stable on the XE family */
/* XL family never shows problems with Player-Missile-artefacts or no-display of them. Also some user reports flickering on XE machines */
/* I do extremly tests on XE machines and this term should be better - tfhh, 25.01.2015 */


 